instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

• (computer science) the process of carrying out an instruction by a computer
  Synonym:execution

双语例句

• This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
  本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。
• The article essentially describes such points as instruction execution and memory management in constructing a virtual running embedded system.
  文中着重介绍了构建嵌入式虚拟运行平台中的指令执行、存储器管理等核心技术问题。
• Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle.
  提出基于指令类型动态分配的译码器设计方案和基于指令执行周期的动态逻辑发射方案。
• This article probes into a kind of encryption method for files, which is different from the usual way. It also studies the encryption method for instruction inverse execution, which means how to use inverse instruction stream to realize the file encryption.
  研究一种打破常规的文件加密方法，指令的逆运动加密方法，即如何采用逆指令流来实现对计算机文件的加密。
• In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
  为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。
• In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
  在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。
• A4-stage instruction pipeline for instruction execution makes at-speed test possible.
  四级指令流水线的引入使全速测试成为可能。
• Research and Analysis of the Value Prediction and Instruction Reuse Techniques in Speculated Execution
  推测执行中值预测与指令重用技术的研究与分析
• But in reality, the upper software drives the underlying hardware, for example different instruction execution and data access affect the underlying hardware circuit directly and result in different power generation.
  但在实际情况中，底层硬件受上层软件驱动，例如不同指令执行和数据存取等软件指令直接影响底层硬件的电路活动，导致不同功耗产生。
• As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
  作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。